Speaker
Description
A LLRF control system for a synchrotron based on MTCA.4 has been developed and operated at WERC. The system was replaced old one consisted of DDS (Direct Digital Synthesizer), DSP (Digital Signal Processor) and analog RF circuits. The new system consists of three AMCs. One is for feedback control of RF frequency and the others are for processing beam position signals. In 2018-2019, we designed and made an FPGA circuit based on the J-PARC LLRF system. From 2020 to 2021, we confirmed the operation of the cavity voltage feedback in the off-beam state. From November 2021, we repeated beam tests to find and correct defects. In parallel with the above, we developed operation interfaces. From October 2023, we began using the feedback control unit for normal operation. This increased the acceleration efficiency from ~70% to ~80%, and the extraction current from ~ 2.5 nA to ~3 nA. Previously, frequency control was performed using B-Clock, but in 2024, adjustment of a frequency pattern using T-Clock was established. From fiscal year 2025, operations using T-Clock patterns will be introduced. In November 2024, COD measurements were performed using the BPM signal processing system. The validity of the measurement results was confirmed by comparing them with measurements using the old system.
