MTCA workshop for accelerator and physics in Japan 2025

27 Aug 2025, 10:00 → 29 Aug 2025, 17:00 Asia/Tokyo

Bldg. #3 Seminar Hall (High Energy Accelerator Research Organization (KEK), Tsukuba Campus)

Registration deadline has been extended to Aug. 18 23:59 JST!
Registration is closed. Thank you for the many registrations!

To presenters who have not submitted an abstract: 

Please send your title and abstract by email.(mtcajp2025[a]ml.post.kek.jp)
For others, if you have any corrections or changes, please also inform us by email.

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The MTCA workshop in Japan 2025 (MTCAWS in Japan 2025) will be held from August 27 to 29 at KEK. MTCA (MicroTCA) is an open-standard embedded computing platform. It is expected to be the new standard platform of the control systems for accelerators and physics. The goal of this workshop is to boost the application of MTCA in Japan by exchanging the information and experiences. The last Japanese workshop in 2021 was held in a virtual format under COVID-19 conditions. The workshop will be held in a hybrid format at KEK with virtual participation via Zoom, so that colleagues outside Japan can join the workshop, while we strongly encourage Japanese colleagues to attend in person. Participants from both of research institutes and industry are welcome. The workshop consists of tutorials and oral presentations. Industry exhibitions and a KEK tour are also planned.

The main topics of the workshop are:
+ Applications in research facilities
+ Applications in industry
+ New Products
+ New Technologies
+ Future of standard and interoperability
+ Software and firmware

Dates: August 27 (Wed) - 29 (Fri), 2025
Venue: 3rd Building Seminar Hall at KEK, Tsukuba, Japan / Zoom (hybrid format)
Registration fee: Free
Official language: English

Important dates:
+ Registration opens: Jun. 20 (Fri)
+ Abstract submission opens:  Jun. 20 (Fri)
+ Registration and abstract submission closes: Aug. 08 (Fri) Aug. 18 (Mon)
+ Workshop dinner: Aug. 28 (Thu)
+ KEK tour: Aug. 29 (Fri)

We would like to encourage your participation.

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Updates:

2025/08/22 Presentation Preparation published.
2025/08/20 Update Timetable, details of Dinner fee & payment published
2025/08/19 Timetable, Exhibitor information, Tour details published

Wednesday, 27 August

14:00 → 14:10 From organizers

Speaker: Fumihiko TAMURA (J-PARC Center, Accelerator Division)

MTCAWSJP_2025_opening.pptx

14:10 → 14:40 Welcome address

Speaker: Takeshi Komatsubara

250827_MTCA-WS_welcome_forupload.pdf

14:40 → 15:40 Industrial Exhibition & coffee break

15:40 → 16:40 Tutorial Lecture: FPGA Development for MicroTCA Platforms: Open-Source Tools and Best Practices

Field-Programmable Gate Array (FPGA) development is a crucial component in the realization of applications based on MicroTCA systems. Engineers and researchers new to this standard often face significant complexities in handling Advanced Mezzanine Card (AMC) modules, particularly concerning interface implementation (e.g., PCIe, Ethernet, Point-to-Point links), algorithm development, and verification. These common challenges frequently lead to duplicated efforts and "re-inventing the wheel" for recurring FPGA development problems. This tutorial will introduce attendees to a suite of existing open-source tools and applications designed to accelerate these development efforts. We will provide practical tips and tricks for the initial bring-up of any AMC board featuring a modern FPGA. The session will feature concrete examples and established solutions deployed in experimental physics facilities across Europe, demonstrating how to avoid common pitfalls and streamline the development lifecycle.

Speaker: Cagil Gumus (DESY)

mtca-ws-japan-2025.pdf

Thursday, 28 August

10:00 → 11:00 Session 1

10:00 Applications of MTCA at J-PARC

The first application of MTCA at J-PARC is the RCS LLRF control system, which was deployed in 2019. Since then, the number of the applications at J-PARC is steadily increasing. The LLRF control systems for MR and Linac are now fully operational. We have several future applications, for example, the digitizer for Linac beam loss monitors and the timing system. The status and future plan of the MTCA application at J-PARC are presented.

Speaker: Fumihiko TAMURA (J-PARC Center, Accelerator Division)

session1_1_MTCAWSJP2025_tamura_J-PARC_applications_v2.pdf

10:20 OPERATION STATUS OF A LLRF CONTROL SYSTEM AT WERC

A LLRF control system for a synchrotron based on MTCA.4 has been developed and operated at WERC. The system was replaced old one consisted of DDS (Direct Digital Synthesizer), DSP (Digital Signal Processor) and analog RF circuits. The new system consists of three AMCs. One is for feedback control of RF frequency and the others are for processing beam position signals. In 2018-2019, we designed and made an FPGA circuit based on the J-PARC LLRF system. From 2020 to 2021, we confirmed the operation of the cavity voltage feedback in the off-beam state. From November 2021, we repeated beam tests to find and correct defects. In parallel with the above, we developed operation interfaces. From October 2023, we began using the feedback control unit for normal operation. This increased the acceleration efficiency from ~70% to ~80%, and the extraction current from ~ 2.5 nA to ~3 nA. Previously, frequency control was performed using B-Clock, but in 2024, adjustment of a frequency pattern using T-Clock was established. From fiscal year 2025, operations using T-Clock patterns will be introduced. In November 2024, COD measurements were performed using the BPM signal processing system. The validity of the measurement results was confirmed by comparing them with measurements using the old system.

Speaker: Tetsuro Kurita (The Wakasa Wan Energy Research Center)

Session1_2_kurita.pdf

10:40 Operational experience of MTCA.4-based BPM electronics for SPring-8

The single-pass BPM electronics at SPring-8 has been replaced by MTCA.4-based electronics. BPM signals are processed by an RTM and sent to a high-speed digitizer AMC. The BPM signal has an RF component synchronized to the acceleration RF frequency of 508.58 MHz. This component is extracted from the filter on the RTM, the signal level is adjusted, and the RF signal is directly sampled by the digitizer. The sampling rate of the digitizer is 363.27 MHz, which is 5/7 of the RF frequency. The sampling clock is generated by a clock eRTM and distributed through an RF backplane for MTCA.4. The acquired data is processed by an FPGA on the digitizer, and the beam position is calculated. This new readout system provides beam position data of both single-pass and COD (Closed Orbit Distortion) in parallel. The new readout system will be utilized for all the BPMs in the SPring-8-II storage ring, which is a low-emittance upgrade of SPring-8. The position resolution of the new BPM system was confirmed to be less than 100 µm for a single-pass mode with a bunch charge of 100 pC, and less than 1 µm for a fast acquisition (10 kHz) COD mode. In this contribution, we present the operational experience of the new BPM readout electronics.

Speaker: Hirokazu Maesaka (RIKEN SPring-8 Center)

Session1_3_MaesakaR1.pptx

11:00 → 11:30 Industrial Exhibition & coffee break

11:30 → 12:30 Session 2

11:30 Application of MTCA to collision feedback system in SuperKEKB

SuperKEKB implements a collision feedback system to maintain stable collision. The system consists of several MTCA boards. This presentation describes the application of MTCA to the feedback system.

Speaker: Hitoshi Fukuma (KEK)

Session2_1_FukumaVer1.pdf

11:50 Operational experience of MTCA.4 modules used at LLRF of SPring-8 storage ring

We had four RF stations in SPring-8 storage ring. We replaced the NIM module based system to MTCA.4 module based system at RF station A in 2018. The replacement of the LLRF system at other three RF stations were carried out step by step. In this talk, operational experience of MTCA.4 modules will be shown.

Speaker: Takashi Ohshima (JASRI)

Session2_2_Ohshima.pdf

12:10 Towards Migration from VME to MicroTCA in Accelerator Control Systems at SuperKEKB and Linac

The VME system has long been used for accelerator controls in SuperKEKB.
However, since this architecture is now outdated, we have been considering migration to a microTCA-based system.
In this talk, we will present the background and criteria for this transition.

Speaker: Hitoshi SUGIMURA (KEK ACCL)

mtcaws2025_sugimura.pdf

12:30 → 14:30 Lunch Break

14:30 → 15:30 Session 3

14:30 Introduction of digitizers with MTCA interface and application specific firmwares

TSPD offers digitizer products with various interfaces. We will introduce the models with MTCA interface, along with application-specific firmware developped for those products.

Speaker: Yoshikazu Kawamata (Teledyne SP Devices)

Session3_1_TSPD_Kawamata.pdf

14:50 A high-speed MTCA.4-based digitizer for the J-PARC MR

J-PARC Main Ring (MR) delivers the 30-GeV protons to the particle physics experiment. Microwave instabilities have been observed in the J-PARC MR during both the acceleration for the beam to the neutrino experiment and the debunching process for the beam to the hadron experiment. Since the instability does not occur every shot, monitoring the waveform of the beam signal for every shot is desired to investigate the source of the instability. Currently, the oscilloscopes are used to monitor and record the waveform of the beam signal. Since the data acquisition from the oscilloscope via Ethernet is not fast enough for the fast repetition cycle of the MR, we introduced an MTCA-4-based high-speed digitizer to record the waveform. The large memory on the module and the data transfer via the PCI Express bus enable us to monitor and record the whole acceleration cycle. In this presentation, we present the current status of the new digitizer in the J-PARC MR.

Speaker: Yasuyuki Sugiyama (KEK/J-PARC)

Session3_2_MTCAWS2025_JP_sugiyama_digitizer.pdf

15:10 MMC Software Engineering: Challenges and Solutions

The Module Management Controller (MMC) is a critical intelligent controller responsible for managing AMC boards. It communicates with the MTCA Carrier Hub (MCH) via the Intelligent Platform Management Bus Local (IPMB-L). Since 2010, we have been developing MMC software for our AMC and uRTM boards. During development, we encountered challenges related to the complex protocols defined in the Intelligent Platform Management Interface (IPMI) specifications, including the AMC, ATCA, and MTCA standards. Additionally, the use of a small microcontroller imposed strict limitations on ROM and RAM capacity, making it difficult to fully implement all required specifications. This presentation provides a concise overview of our experience in developing MMC software.

Speaker: Ryuta Kitagawa (MITSUBISHI ELECTRIC DEFENSE AND SPACE TECHNOLOGIES CORPORATION)

Session3_3_Kitagawa.pdf

15:30 → 16:25 Industrial Exhibition & coffee break

16:25 → 16:30 Group photo

16:30 → 17:00 Keynote Talk: Future Linear Collider and its LLRF system

Speaker: Shinichiro MICHIZONO (KEK)

Keynote_Michizono.pdf

17:00 → 17:20 Session 4

17:00 NAT-MCH Gen4

The 4th generation of NAT-MCH is the successor of the 3rd generation of NAT-MCH, which - after more than 18 years of successful deployments - is coming to its end of life now. The 4th generation MCH provides a lot of improvements and new features and functions, such as 10GbE base switch with 25GbE uplinks, new 40/100GbE fat pipe hub with 10/40/100GbE uplinks, new PCIe Gen 4 fat hub, new CLK module with replacement for IDT multiplexer, new web and harmonized CLI interface in order to name a few. Also, the 4th generation MCH is MTCA.0 Rev 3 compliant and has been designed to meet the upcoming requirements addressed by the next generation of MicroTCA as close as possible already. To ensure product continuity, the family of NAT-MCHs of the 4th generation include ready-to-go products for science and research, similar to the NAT-MCH-PHYs and NAT-MCH-PHYS80. After a short overview comparing the 3rd generation NAT-MCH with its 4th generation, N.A.T. will explain how existing customers can easily migrate to the 4th generation MCH in existing applications.

Speaker: Heiko Koerte (N.A.T.)

Session4_1_NAT_MCH-Gen4.pdf

18:00 → 20:00 Workshop dinner

Friday, 29 August

09:30 → 10:30 Session 5

09:30 Present Status of J-PARC LINAC LLRF (Tentative)

Speaker: Kenta Futatsukawa (KEK)

Session5_1_J-PARC-LINAC_Futatsukawa.pdf

09:50 MicroTCA-based LLRF systems used at the STF at KEK

In this contribution we present the MicroTCA-based LLRF systems used for the STF-II accelerator. At the same facility a vertical test stand for the R&D of superconducting cavities is operated. The over 20-year-old analog control system is being replaced by a MicroTCA.4-based system. We report on the commissioning status of it. In addition to this an outlook for the planned MicroTCA.4-based digital LLRF system for the test of an ILC prototype CM is being presented.

Speaker: Mathieu Omet (KEK)

Session5_2_Talk MTCA WS JP 202508028 OMET v3.pdf

10:10 Automated Passband Mode Resonance Peak Finding Algorithm Using MicroTCA.4-Based Digital LLRF System

The vertical test (VT) stand at the KEK Superconducting RF Testing Facility (STF) uses an analog RF control system which is over 20 years old now. We are currently in the process of replacing this old system with a new digital LLRF system based on the MicroTCA.4 architecture. The digital system also allows for greater flexibility regarding configurability and software automation due to the integration of a CPU in the MicroTCA.4 crate. It is our goal to automate the VT process to improve measurement repeatability, reliability, and speed. One crucial step towards this goal is automated identification of multi-cell (3 and 9-cell) cavity passband modes. To accomplish this, we have developed an automated resonance peak finding algorithm which utilizes broadband noise injection and calculates the FFT spectrum of the cavity response. We have developed a method to combine multiple FFT measurements across different frequency ranges to improve frequency resolution and signal to noise ratio. To demonstrate the capabilities of this method for multi-cell cavity passband mode identification, we have successfully measured all the passband modes of a 3-cell cavity during VT.

Speaker: Eric Viklund (KEK)

Session5_3_Digital LLRF FFT.pptx

10:30 → 11:00 Industrial Exhibition & coffee break

11:00 → 12:20 Session 6

11:00 Upgrade plan of MicroTCA based event timing system at KEK LINAC

VME-based event timing system plays an important role for the synchronization of beam diagnostics and accelerator device control at KEK LINAC. However, with some VME modules approaching its market end-of-life, transitioning to modern platforms like MicroTCA is becoming necessary. We decide to migrate the timing system by focusing on a phased upgrade approach, where new MicroTCA based MRF 300-series timing modules will coexist with and eventually replace the legacy VME timing modules. This talk introduces the plan and current status of timing system upgrade.

Speaker: Di Wang (KEK)

Session6_1_timing_upgrade_diwang.pdf

11:20 Operation status of MTCA.4 based LLRF control system for the J-PARC MR

Speaker: Yasuyuki Sugiyama (KEK/J-PARC)

Session6_2_MTCAWS_JP_2025_MRLLRF_sugiyama.pdf

11:40 Development of MTCA-based boards for the LLRF at the KEK PF 2.5 GeV ring

At the KEK Photon Factory 2.5 GeV ring (PF ring), a new LLRF system was installed in 2023. The new system is composed of digital boards based on the MTCA.4 standard. This presentation will summarise the development of these digital boards.

Speaker: Daichi Naito (KEK)

Session6_3.pptx

12:00 Current Status of the LLRF System for the Muon Linac of g-2/EDM Experiment at J-PARC.

Speaker: Ersin Cicek (KEK)

20250829_MTCAWS_2025_CicekErsin.pdf

12:20 → 12:40 Closing

Speaker: Fumihiko TAMURA (J-PARC Center, Accelerator Division)

MTCAWS_JP_2025_closing_tamura.pdf

14:00 → 17:00 KEK site tour