Name: MTCA workshop for accelerator and physics in Japan
Start: 2021-10-26T10:00:00+09:00
End: 2021-10-28T17:40:00+09:00
Location: Virtual (Zoom)

MTCA workshop for accelerator and physics in Japan

from Tuesday, October 26, 2021 (10:00 AM) to Thursday, October 28, 2021 (5:40 PM)

Monday, October 25, 2021
Tuesday, October 26, 2021

10:00 AM Fumihiko Tamura
Fumihiko Tamura
10:00 AM - 10:10 AM
10:10 AM 加速器に広がるMicroTCAプラットフォーム　～ MicroTCAの基礎と概要～ - 白井野之
加速器に広がるMicroTCAプラットフォーム　～ MicroTCAの基礎と概要～
- 白井野之
10:10 AM - 10:50 AM
10:50 AM AMC の作り方 - 漁師雅次
AMC の作り方
- 漁師雅次
10:50 AM - 11:30 AM
11:30 AM 国産MCHの開発経験談 - 箭原正道 (サンリツオートメイション株式会社)
国産MCHの開発経験談
- 箭原正道 (サンリツオートメイション株式会社)
11:30 AM - 12:10 PM
12:10 PM 昼食休憩
昼食休憩
12:10 PM - 1:30 PM
1:30 PM MTCA シェルフ開発・製作について - 森本正治 (株式会社ユーバー)
MTCA シェルフ開発・製作について
- 森本正治 (株式会社ユーバー)
1:30 PM - 2:10 PM
2:10 PM MTCA.4 規格 RTM、eRTMの製作 - 矢上重男 (株式会社キャンドックスシステムズ)
MTCA.4 規格 RTM、eRTMの製作
- 矢上重男 (株式会社キャンドックスシステムズ)
2:10 PM - 2:50 PM
2:50 PM SPring-8 / SACLA における高周波制御とビーム診断での MTCA.4 の活用 - 前坂比呂和 (理化学研究所放射光科学研究センター)
SPring-8 / SACLA における高周波制御とビーム診断での MTCA.4 の活用
- 前坂比呂和 (理化学研究所放射光科学研究センター)
2:50 PM - 3:30 PM
3:30 PM 休憩
休憩
3:30 PM - 3:50 PM

3:50 PM Zoom 日本語通訳の説明
Zoom 日本語通訳の説明
3:50 PM - 4:00 PM
4:00 PM Electromagnetic Compatibility (EMC) and Analog Design Aspects in MicroTCA Crates (日本語通訳付き) - Frank Ludwig (DESY)
Electromagnetic Compatibility (EMC) and Analog Design Aspects in MicroTCA Crates (日本語通訳付き)
- Frank Ludwig (DESY)
4:00 PM - 4:40 PM
Wednesday, October 27, 2021

10:00 AM Fumihiko Tamura
Fumihiko Tamura
10:00 AM - 10:10 AM
10:10 AM Welcome address - Takashi Kobayashi (Director of the J-PARC Center)
Welcome address
- Takashi Kobayashi (Director of the J-PARC Center)
10:10 AM - 10:40 AM
10:40 AM μTCA(MTCA.0) FPGA-Boards Development and Applications at KEK-Tsukuba - Tetsuya Kobayashi (KEK)
μTCA(MTCA.0) FPGA-Boards Development and Applications at KEK-Tsukuba
- Tetsuya Kobayashi (KEK)
10:40 AM - 11:10 AM
At KEK-Tsukuba Site, Micro-TCA(MTCA.0)-based FPGA boards were developed for LLRF control systems in 2009. EPICS-IOC is embedded into them. Our MTCA-based systems were applied to accelerators at KEK ahead of other facilities in the world, and they are successfully working in the beam operation. In this talk, some reminiscences of our struggles with the development of original FPGA boards will be presented, and MTCA application state in our facilities will be also reported.
11:10 AM Timing synchronization system for beam injection from SACLA to SPRING-8 storage ring - Takashi Ohshima (JASRI)
Timing synchronization system for beam injection from SACLA to SPRING-8 storage ring
- Takashi Ohshima (JASRI)
11:10 AM - 11:30 AM
We developed a timing synchronization system for injection from the linac of the XFEL machine, SACLA, to the storage ring (SR) of SPring-8. This injection scheme is demanded by the low-emittance upgraded ring in the future. Since the RF frequencies of the linac and the SR do not have an integer multiples relation, we have to introduce a new scheme to synchronize the beam ejection timing of the linac to the desired RF bucket timing of the SR. The new system was implemented to the MTCA.4 standard modules. The control of the bucket address is done according to the pre-defined injection table. The system was installed to the linac and the measured timing jitter was better than 4 ps in rms, which was enough to obtain high injection efficiency. This injection scheme has been adopted for the user operation of SPring-8 since February 2020.
11:30 AM MTCA.4 based LLRF control systems for J-PARC synchrotrons - Yasuyuki Sugiyama (KEK)
MTCA.4 based LLRF control systems for J-PARC synchrotrons
- Yasuyuki Sugiyama (KEK)
11:30 AM - 11:50 AM
MTCA.4 based LLRF control systems have been developed for synchrotrons of the Japan Proton Accelerator Research Complex (J-PARC). The J-PARC synchrotrons consist of the Rapid Cycling Synchrotron (RCS) and the Main Ring synchrotron(MR). Since the magnetic alloy loaded untuned RF cavity systems are used in both synchrotrons, multi-harmonic amplitude and phase control is essential and required to compensate a heavy beam loading. A MTCA.4 shelf with the DESY-type RF backplane is employed in developed LLRF control system to fit several AMC boards for controlling RF cavities. The multi-harmonic vector RF voltage control function is implemented in AMC to control the cavity RF voltage. The cavity voltage signal for the vector sum calculation and the beam phase feedback signal are exchanged between AMC boards via the MTCA backplane. The LLRF control system for the RCS was successfully deployed in 2019 and contributed to the achievement of stable acceleration of the high-intensity beam up to the design intensity, 8.3e13 protons per pulse. The prototype system for the MR was tested and used in the beam operation since 2020 to suppress unwanted harmonics. We plan to deploy the developed system to the MR during the shut-down period in 2021.
11:50 AM Lunch break
Lunch break
11:50 AM - 1:30 PM
1:30 PM DMMC Stamp and WIENER power supply - Tomokazu Murakoshi (Embeck)
DMMC Stamp and WIENER power supply
- Tomokazu Murakoshi (Embeck)
1:30 PM - 1:50 PM
DMMC Stamp: DESY microTCA Technology LAB Launch the DMMC-Stamp. Embeck is responsible for domestic sales. We will first introduce you to this wonderful, small component. WIENER Power supply Low Noise 1000W PS for MTCA.4: we will introduce the features and performance.
1:50 PM Next-generation open architecture MTCA field and Vadatech MTCA.4 lineup introduction - Moriaki Hakuta (LHS)
Next-generation open architecture MTCA field and Vadatech MTCA.4 lineup introduction
- Moriaki Hakuta (LHS)
1:50 PM - 2:10 PM
Current status of application fields for open architecture standard products after VME / Compact-PCI and Introducing Vadatech's MTCA product lineup and FPGA-equipped high-speed AD / DA products.
2:10 PM Realization of high precision analog pattern output module by MicroTCA.4 - Naoki Kawamura (Hitachi Zosen Corporation )
Realization of high precision analog pattern output module by MicroTCA.4
- Naoki Kawamura (Hitachi Zosen Corporation )
2:10 PM - 2:30 PM
In the past, bus systems such as VME have been used for accelerator control and other systems that require stability, high reliability, and environmental resistance. For several decades, we have been designing and manufacturing VME bus boards and supplying systems. However, it has been more than 30 years since the birth of the VME standard, and the communication speed of the bus is inferior to that of the VME standard, and there are concerns about product supply in terms of maintainability. This time, we adopted the micro TCA bus standard as a module used in the pattern waveform output unit for controlling the paint bump power supply for J-PARC, which was conventionally built on the VME bus, and produced 2-channel 16-bit DA conversion analog modules as a replacement for the conventional unit. The pattern output board of the micro TCA bus standard makes the pre-set 16-bit data output patterns while synchronizing with the 1MHz clock, and outputs two types of output patterns, current patterns and voltage patterns of the paint bump power supply. This presentation will give an overview of the analog output module applying the micro TCA bus and the performance of the replacement evaluation with a conventional VME system.
2:30 PM Development of a LLRF control system at WERC - Tetsuro Kurita (WERC)
Development of a LLRF control system at WERC
- Tetsuro Kurita (WERC)
2:30 PM - 2:50 PM
A new LLRF control system for the synchrotron at WERC is in under development. The current system consisted of DDS (Direct Digital Synthesizer), DSP (Digital Signal Processor) and analog RF circuits has been working for 20 years with making a continuous improvement in it. However the current system becomes deteriorated and can not be maintained. The new system utilizes modern FPGAs and MicroTCA.4. The new system consists of three AMCs. One is for feedback control of RF frequency and the others are for processing beam position signals. We describe details of the system and the progress of the off-beam commissioning in this report.
2:50 PM Break
Break
2:50 PM - 3:20 PM
3:20 PM Synchronization of several EtherCAT networks by new multi-network EtherCAT AMC client - Herbert Erd (N.A.T)
Synchronization of several EtherCAT networks by new multi-network EtherCAT AMC client
- Herbert Erd (N.A.T)
3:20 PM - 3:40 PM
Certain scenarios in industry and scientific research require to synchronize different EtherCAT networks with a high accuracy. The more precise the time stamp requirements become, the more difficult this task gets using classical solutions. By means of a newly developed AMC module, the time signals can be synchronously fed into and read from up to 8+1 independent EtherCAT networks. This provides a new possibility to connect classical industrial solutions to high performance MicroTCA systems in a flexible and cost-efficient way. The talk will compare this new solution to classical ones and high-light the benefits for users such as the European XFEL, Hamburg, Germany, where it will be used to connect to the installed MicroTCA systems.
3:40 PM More flexible and cost-efficient x86 and non-x86 based compute power for MicroTCA systems - Herbert Erd (N.A.T)
More flexible and cost-efficient x86 and non-x86 based compute power for MicroTCA systems
- Herbert Erd (N.A.T)
3:40 PM - 4:00 PM
One of today’s setback in MicroTCA is the limited availability of (latest) x86 CPU generations in AMC formfactor. To overcome this situation and to provide more flexibility to the market N.A.T has developed a new carrier for COMex modules in AMC format which allows customers to select processing power based on exact needs, i.e. payload or control, from a small 2-core Celeron up to powerful 6 core XEON, made of the latest x86 CPU generation. The new COMex AMC carrier can host COMex modules based on TYPE 6 and 7 and is not limited to CPUs from Intel®. The new CPU carrier in AMC format will provide more flexibility and scalability to MicroTCA systems. It is a logical step in system design, from N.A.T.’s existing NAT-MCH-RTM module to the upcoming requirements addressed by the next generation of MicroTCA, providing more power, more bandwidth and higher bandwidth per AMC.
4:00 PM MTCA.4 Crates: Introduction to the hardware infrastructure - Christian Ganninger (nVent)
MTCA.4 Crates: Introduction to the hardware infrastructure
- Christian Ganninger (nVent)
4:00 PM - 4:20 PM
nVent SCHROFF has committed itself to support the Big Science community with a broad portfolio of MTCA.4 crates as well as a full range of adjacent accessories like AMC front panels, filler panels, air blockers and guide rails. This presentation shows the range of nVent SCHROFF crates from 1U, 3U, and development crates up to the various versions of 12 Slots crates with different options and backplane topologies. In addition, the accessories will be presented and some hints are given on how and when to use filler panels.
4:20 PM Overview of MMC stamp software development kit - Patrick Huesmann (DESY)
Overview of MMC stamp software development kit
- Patrick Huesmann (DESY)
4:20 PM - 4:40 PM
The Module Management Controller (MMC) is a mandatory component of every AMC board. DESY is developing, maintaining and licensing a turn-key MMC solution that is used on several hundred boards in different facilities - on DESY's own products as well as on third-party AMC boards developed by industrial customers and project partners. With the growing number of different boards, a clear separation between common code shared across boards and board-specific code becomes crucial - to keep the codebase maintainable as well as to provide a high-level API for AMC board developers who should be able to focus on their application without having to care about the low-level workings of the MMC. The high-level API makes a software development kit (SDK) possible, which is offered to MMC Stamp System-on-Module customers who wish to customize the pre-programmed firmware according to their needs. This presentation gives a brief overview of the SDK and the high-level API it provides to AMC board developers.
4:40 PM Status and future plans of the MicroTCA.4 compliant LO and CLK generation module - Uros Mavric (DESY)
Status and future plans of the MicroTCA.4 compliant LO and CLK generation module
- Uros Mavric (DESY)
4:40 PM - 5:00 PM
The DRTM-LOG1300 (uLOG) is a MicroTCA.4 compliant LO and CLK generation module. It has been operating on EuXFEL for several years now. Currently other experiments expressed their interest for the LO and CLK generation modules operating at different reference frequencies. However not all the required LO and CLK frequencies can be generated using the currently implemented architecture. In parallel we have started a collaboration with the company KVG Quartz Crystal Technology GmbH to produce and test the newly produced modules. In this talk we will present other possible LO and CLK generation techniques which can provide LO and CLK signals with reference frequencies 500 MHz, 3 GHz and others. It is possible to order all these modules from KVG Quartz Crystal Technology GmbH.
Thursday, October 28, 2021

10:00 AM Fumihiko Tamura
Fumihiko Tamura
10:00 AM - 10:10 AM
10:10 AM MicroTCA.4 projects at Sirius light source - Daniel Tavares (Sirius/LNLS )
MicroTCA.4 projects at Sirius light source
- Daniel Tavares (Sirius/LNLS )
10:10 AM - 10:40 AM
The MicroTCA.4 standard has been employed at Sirius light source for a few accelerator systems: electron and photon BPM electronics, fast orbit feedback and timing receiver for distributed power supplies. In total 22 MicroTCA.4 crates run routinely at Sirius for users operation. This talk will describe the existing systems and short term plans. Special focus will be given to the issues found and lessons learned.
10:40 AM Survey on MTCA in Japanese accelerators - Fumihiko Tamura (J-PARC Center)
Survey on MTCA in Japanese accelerators
- Fumihiko Tamura (J-PARC Center)
10:40 AM - 11:00 AM
MTCA is expected to be the next-generation platform for accelerator controls and many applications of MTCA are found in the acclerators in the world, while it seems slow to spread to the Japanese accelerator facilities. To investigate the reason, a small survey was performed in 2020 among KEK and J-PARC members, who are working for LLRF, monitors, and control systems. The survey results and the issues that were identified, are reported.
11:00 AM Timing and low level RF control system of new injector LINAC for NEW SUBARU - Eito Iwai (JASRI)
Timing and low level RF control system of new injector LINAC for NEW SUBARU
- Eito Iwai (JASRI)
11:00 AM - 11:20 AM
A new linear accelerator was constructed for the New SUBARU (NS), a 1.5 GeV synchrotron radiation facility. The accelerating frequencies used at the new linac are 238 MHz, 476 MHz, 2856 MHz (SB), and 5712 MHz (CB). The required accuracy for the amplitude and phase of the accelerating field are 8E-4 and 0.2 degree, respectively in the most severe case. Also, the master trigger of the linac must be synchronized with both the aimed bucket timing of the ring and the linac master clock. To fulfill these requirements, the timing system and Low-Level RF (LLRF) control system were developed using the modules of Micro Telecommunication Computing Architecture 4 (MTCA.4) standard. The master trigger and the clock of the linac are generated at the master unit located near the LLRF station of the ring, and are delivered to four LLRF subunits of the linac through the optical links. The amplitude and phase of the accelerating field are controlled based on In-phase and Quadrature (IQ) scheme. The achieved stabilities in rms are 7E-4 in amplitude and 0.2 degree in phase, which satisfy the requirements. The operation of the NS has been carried out stably since April 2021 without any significant faults.
11:20 AM Uniform communication over the MTCA interconnect and network - Kazuro Furukawa (KEK)
Uniform communication over the MTCA interconnect and network
- Kazuro Furukawa (KEK)
11:20 AM - 11:40 AM
A low-level RF controller has been developed for the accelerator controls for SuperKEKB, Super-conducting RF Test facility (STF) and Compact-ERL (cERL) at KEK. The feedback mechanism will be performed on Virtex-5 FPGA with 16-bit ADCs and DACs. The card was designed in the form-factor of an advanced mezzanine card (AMC) for a MicroTCA shelf. An embedded EPICS IOC on the PowerPC core in FPGA will provide the global controls through channel access (CA) protocol on the backplane interconnect of the shelf. No other mechanisms are required for the external linkages. CA is exclusively employed in order not only to make the AMC cards to communicate with each other, but also to communicate with central controls and with an embedded IOC on a Linux-based PLC for slow controls.
11:40 AM LLRF system based on MTCA.4 boards for the J-PARC Linac - Kenta Futatsukawa (KEK)
LLRF system based on MTCA.4 boards for the J-PARC Linac
- Kenta Futatsukawa (KEK)
11:40 AM - 12:00 PM
In the J-PARC linac, the low-level radio frequency (LLRF) system with the digital feedback (DFB) and the digital feedforward (DFF) based on the cPCI platform was adopted for the satisfaction of amplitude and phase stabilities. It was operated without serious problems. However, it has been used since the beginning of the J-PARC and are more than fifteen years into the development. The increase of the failure frequency for this system is expected. In addition, it is difficult to maintain it for some discontinued boards of DFB and DFF and the older OS and developing environment of software. Therefore, we had developed the new digitizer based on MTCA.4 boards for the LLRF system of the next generation. We installed and operated the seventeen digitizers at DTL3 and SDTL stations from the summer shutdown of 2020. In addition, we will install the three digitizers and one the MTCA.4 system, which is used to control four stations at MEBT1, in this summer. The project and the status of the LLRF system based on MTCA.4 for the J-PARC linac are introduced.
12:00 PM Lunch break
Lunch break
12:00 PM - 1:30 PM
1:30 PM Status of MTCA.4 standard based LLRF control board for the linear accelerator of the STF-2 and the ILC - Toshihiro Matsumoto (KEK)
Status of MTCA.4 standard based LLRF control board for the linear accelerator of the STF-2 and the ILC
- Toshihiro Matsumoto (KEK)
1:30 PM - 1:50 PM
In the International Linear Collider (ILC), the RF power generated with a single RF source (10 MW multi-beam klystron) is supplied to 39 superconducting cavities, and the amplitude and phase of each cavity are operated by vector sum-feedback control to keep the accelerating electric field and phase constant in single RF unit. At the Superconducting Test Facility (STF) of the High Energy Accelerator Research Organization (KEK), the STF-2 accelerator has been constructed and operated for the research and development of the ILC. In order to build a minimum configuration of the low-level RF control system for the ILC, the MTCA.4 standard based digital control board using ZYNQ have been developed for the LLRF system of the STF2 accelerator. The present status of the digital control board developed at STF and the future plan for ILC are reported.
1:50 PM Adoption of the micro-TCA to the next KEK-PF LLRF system - Daichi Naito (KEK)
Adoption of the micro-TCA to the next KEK-PF LLRF system
- Daichi Naito (KEK)
1:50 PM - 2:10 PM
We plan to replace the low-level RF (LLRF) system at the KEK-PF. The present LLRF system is composed of analog modules, while the new system will be composed of digital boards which are based on the μTCA.4 standards. On the other hand, we will also adopt the μTCA to the monitor system for the transient beam loading effect. In this presentation, we introduce the present RF system, the overview of the new LLRF system, and the monitor system.
2:10 PM Utilization of a unique MicroTCA.4-based digitizer for monitoring comb-like beam at the J-PARC Linac - Ersin Cicek (KEK)
Utilization of a unique MicroTCA.4-based digitizer for monitoring comb-like beam at the J-PARC Linac
- Ersin Cicek (KEK)
2:10 PM - 2:30 PM
The J-PARC linac beam pulse, formed by a chopper system placed at the MEBT, consists of a series of intermediate pulses with a comb-like structure synchronized with the rf frequency of the rapid cycling synchrotron (RCS). With a general-purpose digitizer, performing signal processing depending on the presence or absence of such an intermediate pulse is challenging. Besides, monitoring the entire macro pulse cannot be achieved on the current digitizer during the beam operation. However, sequentially measuring and monitoring the comb-like beam, stable operation with less beam loss can be achieved even at higher beam intensity in the J-PARC. To this end, a beam monitor digitizer, including a digital signal processing function, that complies with the MicroTCA.4 (Micro Telecommunications Computing Architecture.4) standard has been developed. We present the architecture and implementation of the beam monitor digitizer within this paper.
2:30 PM Planned upgrade of the LLRF system at the STF vertical test stand at KEK - Mathieu Omet (KEK)
Planned upgrade of the LLRF system at the STF vertical test stand at KEK
- Mathieu Omet (KEK)
2:30 PM - 2:50 PM
The RF system currently used at the vertical test stand at the Superconducting RF Test Facility (STF) at KEK was established more than two decades ago and is all analog. It was decided to upgrade the controller part with a state-of-the-art MicroTCA.4-based LLRF system, allowing self-excited loop (SEL) operation. The realization of this upgrade is planned to be performed in collaboration with DESY.
2:50 PM Break
Break
2:50 PM - 3:20 PM
3:20 PM 4th Generation NAT-MCH - Herbert Erd (N.A.T)
4th Generation NAT-MCH
- Herbert Erd (N.A.T)
3:20 PM - 3:40 PM
After more than 15 years and the 3rd MCH generation being currently deployed, the next generation 4 MCH is will become available soon, providing new features and functions. N.A.T will explain how to transit from today’s MCH will to the 4th generation MCH and what the differences and benefits are. Also, the new generation MCH is designed to meet the upcoming requirements addressed by the next generation of MicroTCA, providing more power, more bandwidth and higher bandwidth.
3:40 PM Digitizers for Big Physics - Kacper Matuszynski (Teledyne SP Devices )
Digitizers for Big Physics
- Kacper Matuszynski (Teledyne SP Devices )
3:40 PM - 4:00 PM
Teledyne SP Devices provides world-leading modular data acquisition systems. As a long-term partner of MicroTCA Technology Lab, it offers various solutions in µTCA.4 form. Apart from getting a brief overview of the existing portfolio of products, you will get a glimpse of future developments. New functions and implementations will be highlighted and discussed. For example, a new way to take benefit of open FPGA architecture by defining a custom algorithm for advanced trigger requirements. We empower engineers and scientists to capture complex data enabling discovery and differentiated products.
4:00 PM Experience with MTCA.4 LLRF systems at DESY - Christian Schmidt (DESY)
Experience with MTCA.4 LLRF systems at DESY
- Christian Schmidt (DESY)
4:00 PM - 4:20 PM
The first MTCA.4 LLRF system at DESY has been tested at the Free Electron LASer in Hamburg FLASH back in 2010. Since then, more and more accelerator facilities within DESY have been equipped with this technology. Today, the European XFEL is operated with a LLRF system consisting of more than 50 MTCA.4 crates. Maintaining all facilities in a twenty-four-seven on-call service allowed us to gain a lot of experience with these system over the last years. Especially the operation in a radiation prone and non-accessible environment demands a continuous improvement of the reliability and development of automation routines. As a next step an upgrade of parts of the LLRF systems at FLASH is planned which are in operation since almost 10 years.
4:20 PM Development of the MicroTCA specification: Preparing the next generation - Kay Rehlich (DESY)
Development of the MicroTCA specification: Preparing the next generation
- Kay Rehlich (DESY)
4:20 PM - 4:40 PM
To keep the MicroTCA standard viable over many years it must follow the development of technology. A PICMG working group was formed to incorporate faster Ethernet and PCIe communication into the standard. This talk will discuss the direction and challenges of the next generation MicroTCA standard.
4:40 PM Fumihiko Tamura
Fumihiko Tamura
4:40 PM - 5:00 PM